HIGH-LEVEL DESIGN  | PRODUCTS

Cynthesizer is the first high-level solution that integrates ESL design with block-level implementation. With TLM Synthesis and its unique transaction-level platform, Cynthesizer provides a way to unify the work and expertise of system architects, software developers, and hardware block designers.

TLM Synthesis allows transaction-level descriptions to be the link between TLM system-level design and the block-level implementation flow. Algorithms are written at the transaction level, communicating with the rest of the system through abstract interfaces.

With the combined use of Cynthesizer's TLM Synthesis and modular interface capability, a single set of source code is used for the design and for the testbench throughout the design flow. As a result, it eliminates redundant modeling efforts while maintaining functional consistency across development teams.

Cynthesizer integrates with any TLM API, making it easy to deploy with your chosen TLM methodology and accomplish the following:

• Switch automatically between TLM and pin-level interfaces
• Try pin-level interfaces with different characteristics without changing source code
• Maintain modeling consistency between ESL and implementation flows
• Explore system communication options using high-speed abstract communication
• Leverage behavioral IP primitives and interfaces to create complex blocks
   

Synthesize What You Verify

Unlike other synthesis solutions that generate TLMs from an algorithm, using the same source as the input to both high-level synthesis and verification provides the added confidence that the final implementation will meet your design requirements.

The transaction-level support delivered with TLM Synthesis enhances your ability to use the same testbench for pin-level and RTL verification. Effort spent on transaction- and pin-level verification can be directly reused to ensure the functional integrity of the behavior in the resulting RTL.

The results:

• Block designers using transaction-level interfaces will experience functional simulation speeds 5X to 10X faster than pin-level behavioral simulation or 50X to 200X faster than RTL simulation.
• System architects are able to link to a block implementation flow with configurable interfaces.
• Software developers get started earlier in the design project.
   

Leverage Transaction-level IP

TLM Synthesis includes a transaction-level interface IP using the OSCI TLM library to accompany the pin-level interface IP included with Cynthesizer. These include:

• TLM versions of Cynthesizer streaming interfaces
• TLM versions of standard memories
• TLM versions of synthesizable FIFOs
• Inline hierarchical channels

Together, TLM Synthesis and pin-level modular interfaces provide a foundation to quickly implement a broad range of designs without spending time on low-level interface details. As a result, you are able to develop complex SoC derivatives at a fraction of the cost and time compared to conventional block-based design methods.

Find out more:
Cynthesizer

TLM Synthesis Datasheet