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HIGH-LEVEL DESIGN  | PRODUCTS

Cynthesizer 5

 

Cynthesizer 5 is the next generation of high-level synthesis technology. It includes ideas and experience from more than a decade of production SystemC high-level synthesis deployment. With Cynthesizer 5, design teams can quickly create high-quality RTL implementations from highly abstract SystemC models. The SystemC models can be easily created using the new Cynthesizer Workbench SystemC IDE, retargeted to new technology platforms, and reused more easily than traditional hand coded RTL. And, Cynthesizer 5 will allow designers to actively make tradeoffs to power in addition to area and performance from right within the high-level synthesis environment.

Cynthesizer 5 redefines high-level synthesis and will help you get designs done more quickly and with better results.

Benefits

  • Quickly create high-quality RTL from abstract SystemC models
  • Reduce power usage and explore area, performance, and power tradeoffs
  • Improve design and verification time
  • Create truly reusable designs by focusing on function instead of implementation

Cynthesizer's "C5" Synthesis Core

Forte's new "C5" synthesis core combines the scheduling and allocation phases of the tool, improving predictability and quality of results. New scheduling algorithms allow Cynthesizer to quickly test multiple design microarchitectures and schedules to find the best possible area, performance, and power based on the designers constraints. The new C5 core improves area results 9% on average compared to previous Cynthesizer releases.

Cynthesizer Low Power

With Cynthesizer 5, design teams can automate complex low power optimizations that are often difficult or impossible to realize with hand-coded RTL. Designers can use Cynthesizer's design exploration capabilities to trade off area, performance, and power for a given set of design constraints.

  • HLS-optimized clock gating technology
  • Finite state machine (FSM) optimization
  • Memory accesses optimized for performance or power.
  • シ and ス speed memory architectures
  • Low power memory modes
  • Clock domain crossing circuitry for designs with multiple clock speeds
  • RTL coding techniques optimized for downstream RTL tools
  • Integrations with popular RTL power analysis and optimizations products.

Combined, these new optimizations can yield power reductions of 60% or more depending on the design.

Cynthesizer Workbench

The Cynthesizer Workbench graphical user interface included with Cynthesizer 5 includes a SystemC Integrated Development Environment (IDE), making SystemC development easy and intuitive for new users and advanced users alike. Beyond typical IDE features, the Cynthesizer Workbench also provides several SystemC design "kick-starters" to quickly create new models using pre-defined templates to reduce design and debug time.

The internals of the Cynthesizer Workbench have also been completely redesigned to allow faster design, debug, and analysis of SystemC models and the resulting RTL designs. The analysis environment includes SystemC and RTL source linking, waveforms, and other tools to optimize design results.

CynWare IP

Cynthesizer 5's CynWare SystemC IP library and CynWare Interface Generator™ give designers synthesizable building blocks to jumpstart their designs. Since these pre-designed elements are implementation independent, they are re-targetable to different processes or QoR targets without performance or area penalties. The result is truly reusable design IP that accelerates the design and verification process.

The CynWare IP library contains high speed simulation models and bit-accurate synthesizable models for all IP.

  • Floating point datatypes available in IEEE754 single and double precision as well as other combinations of exponent and mantissa width defined by the user
  • User configurable connectivity interfaces such as line buffer, circular buffer, trigger-done, streaming data, FIFO-based, and memory interfaces.
  • Clock domain crossing (CDC) circuitry for multi-clock designs
  • Specialized communication interfaces, including frame buffers and bus interfaces for connection using the ARM® AMBA® AXI™ and AHB™.

Datapath Optimization

Forte's patented DpOpt technology can automatically identify optimization opportunities in the high-level SystemC design and synthesize optimized custom datapath components to meet the need. This allows designers to reduce circuit area and power and achieve circuit speeds unachievable through other means.

  • Patented datapath architectures provide
  • Advanced datapath synthesis techniques
  • Fully automatic or user-controllable

Cynthesizer Ecosystem

Forte's support of industry standards eases the adoption of new technology and protects design tool investments over time.

Forte partners with numerous EDA companies to deliver complete design solutions so that our common customers can derive the benefits of using products and technologies that best meet the needs for the production design flows.

Forte is a member of EDAC and an active member of Accelera with a seat on the Board of Directors.

 

 

PDF Format:
Cynthesizer Datasheet
 

Find out more:
TLM Synthesis


 




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