overview

Cuts IP Development from Months to Weeks

With Cadence® Stratus™ High-Level Synthesis (HLS), engineering teams can quickly design and verify high-quality RTL implementations from abstract SystemC™, C, or C++ models. The models can be easily created using the Stratus integrated design environment (IDE). Stratus synthesizable IP for SystemC provides simulation and synthesis models for common bus-based and point-to-point communication protocols as well as common mathematical operations and datatypes.​

Leveraging the Genus™ Synthesis and Joules™ RTL Power engines inside of Stratus HLS, the power, performance, and area (PPA) results are typically equal to or better than those achieved with hand-coded RTL. Front-end designers get high-quality PPA estimates through turnkey integration with the Cadence digital flow.​

With Stratus HLS, SystemC models can be retargeted to new technology platforms and reused more easily than traditional hand-coded RTL. The Stratus graphical user interface (GUI) and Tcl API also allow designers to quantitatively evaluate tradeoffs between the PPA from within the high-level synthesis environment. ​

Stratus HLS automates the design and verification flow of hundreds of blocks from transaction-level modeling (TLM) to gates. In addition, Stratus HLS helps with the real-world issues of engineering change orders (ECOs) and routability, both of which normally occur much later in the flow, through tight integration with the full Cadence tool flow.

Users have reported productivity as high as 2 million verified gates/designer/year, compared to 200,000 with the traditional RTL flow. For more details, read the Stratus HLS datasheet.

Key Benefits

Enabling a Faster Path to Verified, High-Quality RTL Implementations from Abstract SystemC, C, or C++ Models

Superior PPA

Stratus HLS gives engineering teams the ability to explore hundreds of micro-architectures in a fraction of the time it takes to write and verify a single RTL description. With automated exploration and optimization, designers can quickly find the most optimal implementation.

Ease of Technology Re-Targeting

Stratus HLS starts with transaction-level SystemC, C, or C++ descriptions. Because the micro-architecture details are defined during HLS, the source description is significantly easier to write and re-target, making your IP significantly more portable across different technologies.

Productivity

Stratus HLS is highly productive and can be used interactively or via batch runs controlled via Tcl scripts. Users can define a range of constraints and automatically run high-level synthesis and adjacent tools like simulation, power analysis, and logic synthesis.

customer success

Learn how our customers use Stratus HLS to easily explore and optimize power, performance, and area while accelerating their IP development process.

Designing an Automotive Graphics Display Controller with Stratus HLS

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0-60 in 2 seconds: Accelerating an AI chip startup with Cadence-Hosted Design Solutions

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A High Level Synthesis (HLS) Design Flow for Scaling to Multiple IP, SoC, and Process Targets

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Coverage Closure for HLS-Based Design IP

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High-Level Synthesis Models in Pre-Silicon Verification

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HLS enables ML-assisted Architectural Exploration

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Designing a “First-Time-Right” Wi-Fi HaLow Baseband in less than 6 Months

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Design implementation of technology IP using High-Level Synthesis

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Latency-Constrained Design for a Display Stream Compression Decoder with Stratus HLS

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A PPA Coherent Full Flow from High-Level Synthesis Through Physical Implementation

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Entering the world of High-Level Synthesis - What we have learned and experienced

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High-Level Synthesis will supercharge your IP development

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High-Level Synthesis for Low-Power

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Resources

Stratus-Joules Solutions: Achieving Energy-Efficient Allocation
Whiteboard Wednesdays - Low-Power SoC Design with High-Level Synthesis
UCLA leverages high-level synthesis to make rapid architecture trade-offs
NTHU Makes a Human-Like Robot Arm with Stratus HLS and Innovus Implementation
EEJournal Chalk Talk: TensorFlow to RTL with High-Level Synthesis
Whiteboard Wednesdays - TensorFlow to RTL with High-Level Synthesis
Cadence and Mathworks Collaborate to Speed Chip Design
CadenceTECHTALK: From MATLAB to Optimized RTL in Minutes
Digital Implementation and Signoff
CadenceTECHTALK: An AI/ML-driven High-Level Synthesis Solution
Cadence Stratus MATLAB Integration Flow Meeting 5/5/23
From MATLAB to Optimized RTL in Minutes
CadenceTECHTALK: Stratus for High-Performance Mathematical Operations
CadenceTECHTALK: Managing ECO's in Stratus High-Level Synthesis
CadenceTECHTALK: What's New in Stratus High-Level Synthesis
Driving Low-Power Design with High-Level Synthesis
Designing an Automotive Graphics Display Controller with Stratus HLS
From TensorFlow to RTL in three months
0-60 in 2 seconds: Accelerating an AI chip startup with Cadence-Hosted Design...
A High Level Synthesis (HLS) Design Flow for Scaling to Multiple IP, SoC, and...

Related products

Genus Synthesis Solution
Joules RTL Power Solution