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Behavioral synthesis is the enabling technology for implementing a
practical methodology for high-level design. It fits in with existing
design flows and can be selectively applied to portions of a design that
will derive the greatest benefit from the using a higher level of
abstraction and the automation that it provides.
 Behavioral
synthesis allows design at higher levels of abstraction by automating the
translation and optimization of a behavioral description, or high-level
model, into an RTL implementation. It transforms un-timed or partially
timed functional models into fully timed RTL implementations. Because a
micro-architecture is generated automatically, designers can focus on
designing and verifying the module functionality. Design teams create and
verify their designs in an order of magnitude less time because it
eliminates the need to fully schedule and allocate design resources with
existing RTL methods. This behavioral design flow increases design
productivity, reduces errors, and speeds verification.
The behavioral synthesis process incorporates a number of complex
stages. This process starts with a high-level language description of a
module's behavior, including I/O actions and computational functionality.
Several algorithmic optimizations are performed to reduce the complexity of
a result and then the description is analyzed to determine the essential
operations and the dataflow dependencies between them.
The other inputs to the synthesis process are a target technology
library, for the selected fabrication process, and a set of directives that
will influence the resulting architecture. The directives include timing
constraints used by the algorithms, as they create a cycle-by-cycle
schedule of the required operations. The allocation and binding algorithms
assign these operations to specific functional units such as adders,
multipliers, comparators, etc.
Finally, a state machine is generated that will control the resulting
datapath's implementation of the desired functionality. The datapath and
state machine outputs are in RTL code, optimized for use with conventional
logic synthesis or physical synthesis tools.
Find out more about high-level design and behavioral synthesis with
Cynthesizer.
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